The present invention relates generally to semiconductor device fabrication and, more particularly, to electrostatic discharge (ESD) devices for protecting an integrated circuit, methods of fabricating an ESD protection device, and design structures for an ESD protection device.
Modern electronics achieve high levels of functionality in small form factors by integrating multiple functions onto a single chip. A common fabrication process that allows high levels of integration at a relatively low cost is complementary metal-oxide-semiconductor (CMOS). CMOS processes build a combination of p-type and n-type metal-oxide-semiconductor field-effect transistors (MOSFETs) to implement logic gates and other types of digital circuits, as well as analog circuits.
Chips may be exposed to ESD events leading to potentially large and damaging currents within the integrated circuit. Increasing integration densities and performance demands on CMOS chips have resulted in reduced device dimensions, which has increased the susceptibility of integrated circuits to ESD events. Manufacturers, assemblers, and users of integrated circuits must take precautions to avoid unintentionally causing ESD events. For example, ESD prevention can be incorporated into the integrated circuit and may include special design techniques for I/O pins and pads, as well as supply pads, to prevent damage to the chip during handling between the time that the chip is manufactured until the time that the chip is installed on a circuit board and while the chip is installed on the circuit board. ESD protection circuits typically function by directing the current of an ESD event away from the internal circuits of the chip.
Because the performance demands on ESD circuits have increased as CMOS device dimensions have become smaller, ESD circuits have not enjoyed the same reductions in required chip area as other types of CMOS circuits. The increase in the relative area of ESD protection circuits with respect to the protected circuits has resulted in ESD protection circuits typically requiring a larger percentage of overall chip area as CMOS device dimensions have been reduced.
Therefore, improved ESD protection devices, methods of fabricating ESD protection devices, and design structures for ESD protection devices are needed for protecting integrated circuits against ESD events.